(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to a method whereby Plasma Polymerized Methylsilane (PPMS), a photosensitive polymer, forms an oxide layer, Plasma Polymerized Methylsilane Oxide (PPMSO), when exposed to UV light which forms the top insulating layer of a dual damascene insulating layer structure.
(2) Description of Prior Art
In the fabrication of semiconductor integrated circuits the dual damascene process is well known in the fabrication of multi-level conducting metal lines and interconnects.
Related patents teach various methods of photolithography processes to pattern metal lines both with and without dual damascene processing; but these methods do not cover the present invention which consists of using PPMS, a photosensitive polymer with dual damascene CMP processing.
U.S. Pat. No. 5,100,764 to Paulson et al teaches a method whereby sol gel, a colloidal suspension is used to form metal lines. A thin film of sol gel containing titanium, which is UV photo active, is exposed to UV activating the photo active compound which is then used to pattern the metal lines.
U.S. Pat. No. 5,487,967 to Hutton et al describes a photolithography process using a silylated resist that reacts with either exposed or unexposed regions of resist. The silylated resist is exposed to RIE and forms an "in situ" silicon dioxide etch mask, for precise image patterning from resist to substrate.
U.S. Pat. No. 5,591,676 to Hughes et al teaches a method of making a semiconductor device having a low permittivity dielectric. A fluorinated polymer layer is deposited on a metal, semiconductor or nonmetallic surface. The fluorinated polymer is heat treated and patterned by photolithography to form vias and then covered with a metal interconnect layer.
U.S. Pat. No. 5,689,140 to Shoda describes a method of forming studs and interconnects in multi-layered semiconductor devices. A dual damascene process is described with adhesion layers for each conductive layer.
U.S. Pat. No. 5,635,423 to Huang et al describes a dual damascene process to form multilevel metallization and inter-connect structures. An etch stop is described between the first and second insulating layers for via and trench patterning.
U.S. Pat. No. 5,705,849 to Zheng et al teaches a method for manufacturing an antifuse structure. A dual damascene process is described whereby structures comprising a pair of alternating layers of silicon nitride and amorphous silicon are sandwiched between two dual damascene connectors.
U.S. Pat. No. 5,041,361 to Tsuo describes an oxygen ion-beam lithographic patterning method using low-energy oxygen ion beams to oxidize amorphous silicon at selected regions. The non-oxidized regions are removed by etching in an RF excited hydrogen plasma.